/************************************************************\
**	Copyright (c) 2012-2024 Anlogic Inc.
**	All Right Reserved.
\************************************************************/
/************************************************************\
**	Build time: Aug 30 2024 23:01:55
**	TD version	:	5.9.122301
************************************************************/
`timescale 1 ns / 1 ps
module soft_fifo
(
  input                         rst,
  input                         clkw,
  input                         clkr,
  input                         we,
  input   [7:0]                 di,
  input                         re,
  output  [7:0]                 dout,
  output                        valid,
  output                        full_flag,
  output                        empty_flag,
  output                        afull,
  output                        aempty,
  output  [6:0]                 wrusedw,
  output  [6:0]                 rdusedw
);

  soft_fifo_al_696cf75d8274
  #(
      .DATA_WIDTH_W(8),
      .DATA_WIDTH_R(8),
      .ADDR_WIDTH_W(7),
      .ADDR_WIDTH_R(7),
      .AL_FULL_NUM(125),
      .AL_EMPTY_NUM(2),
      .SHOW_AHEAD_EN(0),
      .OUTREG_EN("NOREG")
  )soft_fifo_al_696cf75d8274_Inst
  (
      .rst(rst),
      .clkw(clkw),
      .clkr(clkr),
      .we(we),
      .di(di),
      .re(re),
      .dout(dout),
      .valid(valid),
      .full_flag(full_flag),
      .empty_flag(empty_flag),
      .afull(afull),
      .aempty(aempty),
      .wrusedw(wrusedw),
      .rdusedw(rdusedw)
  );
endmodule
